This invention relates to electronic circuit design tools and methodology (expressed as software) that are typically used to capture the design intent and the specific circuit behavior during the design of a circuit. These tools are also used to communicate the design intent and the circuit behavior between a circuit designer and other technical personnel such as design team member. To make the process easier, textual and graphical tools are embedded in these circuit design tools so as to enhance the understanding and visualization of various aspects of the circuit design. These textual and graphical tools provide an interface in order to display waveforms of various signals and in order to highlight various characteristics that are associated with the circuit design. To display waveforms these tools make use of various kinds of timing waveform diagrams, finite state machine transition diagrams, process flowcharts, etc. Indeed, such graphical representations are standard methods that are currently being used in the circuit design industry. Computer Aided Design (CAD) environments combine the design tools with the graphical tools for this purpose. CAD tools typically provide software-automated environments in order to enable communication between a designer and various kinds of computer-related tools, and by doing so, the designer is able to capture, analyze, and manipulate the design data more effectively and efficiently.
As the complexity in circuit design has increased over the last 30 years, there has been a corresponding improvement in various kinds of verification and debugging techniques (for circuit design). In fact, these verification and debugging techniques have evolved from relatively simple transistor circuit-level simulation (in the early 1970s) to logic gate-level simulation (in the late 1980s) to the current art that uses Register Transfer Language (RTL)-level simulation. RTL is a hardware description language (HDL) used in describing the registers of a computer or digital electronic system, and the way in which data is transferred between them.
Contemporary verification and debugging tools use various levels of abstraction for defining design specification. These abstractions are written using high-level description languages. High-level description languages provide a number of functionalities for analyzing and verifying the design while performing simulation. For example, a designer can navigate the design hierarchy, view the RTL source code, and set breakpoints on a statement of the RTL source code to stop the simulation. Also, line numbers are provided in the RTL source code to identify different lines and statements. Further, the verification and debugging tools often support viewing and tracing variables and some times even signal values. These RTL simulation tools typically also offer these and other types of RTL debugging functionalities.
Recent system chip designs exceed a million or more gates. This kind of complexity requires even more abstract design definition (at the RTL-level) than was available in the past, and such a definition may be difficult to manage. Hence, this has led to the development of a behavior-level modeling, which in turn, allows a designer to define system functionality at a higher level of behavior abstraction.
The abovementioned verification and debugging tools (also referred to as RTL Simulators) operate on a digital representation (or a Simulation Model) of a circuit, a list of inputs, and data regarding the performance characteristics of the circuit elements. These tools generate a numerical representation of the circuit response, which can be viewed on a display screen in graphical form.
The verification and debugging tools as mentioned above typically follow a design flow. This design flow comprises creation of a circuit design at the RTL level followed by its verification using the RTL Simulator. This verification results in the generation of a database, which includes the verification results. This database can be then used for providing information regarding the behavior of the designed circuit. Simulation can be performed at greater speeds using gate-level simulators, hardware Accelerators or software simulators called Emulators. Gate-level simulation involves synthesizing the RTL source code into a gate-level “netlist”. A netlist is a list of components such as gates, flip-flops, etc. and describes the properties of the components and the connections between them. The gate-level netlist can be then verified using a software gate-level simulator or by converting the gate-level netlist into a format suitable for programming an Emulator, a hardware Accelerator, or a rapid-prototyping system so that the circuit specification can take an actual operating hardware form. Accelerators are hardware elements designed for performing special purpose computation required in circuit simulation. Accelerators perform computation that is much faster than software simulators. However, the ability of Accelerators to debug the design at the gate level is severely limited in comparison with software simulators.
As mentioned above, design flow begins with creation of circuit design at the RTL level. Circuit design is created using the RTL level source code. The RTL source code is specified according to Hardware Description Language (HDL) such as Verilog HDL or VHDL. Circuit designers use high-level hardware description languages because of the size and complexity of modern integrated circuits. Circuit design in high-level language is implemented using computer-implemented software applications. These applications enable a user to dynamically review various design facets. Also, these applications enable a user to utilize text-editing and graphical design tools to create HDL-based design.
In the design flow, creation of the RTL source code is followed by verification so as to check if the RTL source code meets the design specifications. This is done using a “Test Bench” or constraints and requirements. The verification method involving the use of RTL source code and Test Bench is referred to as Simulation process. The Test Bench contains a subset of all possible inputs to the circuit/logic. For an ‘n’ input circuit, there are 2n possible inputs at any given time. For large n, e.g., for a complex design, the number of possible input sequences becomes prohibitively large. To simplify this, only a subset of all possible inputs is described in any given test bench. The verification method involving RTL source code and constraints is referred to as Model Checking method. Constraints refer to design constraints, i.e. specifications to be satisfied by the circuits. Intensive mathematical properties are used to define circuit specifications in pure mathematical terms. This results in the generation of all possible valid inputs for a given circuit and it is akin to exhaustive simulation, i.e. testing the circuit for all possible inputs.
The simulation process is simple but doesn't verify the circuit behavior for all possible combinations of inputs. Hence, simulation is not very reliable especially for complex design (wherein large combinations of inputs are possible). The Model Checking method is more exhaustive but utilizes intensive mathematical calculations to verify the circuits.
Results of the verification using the method of either Model Checking or Simulation are stored in a database. This database includes simulation results and design data such as component instances, component pins, routing wire connections, information regarding the buses, etc. The database can be used by a graphical interface to generate timing waveforms for various signals defined in the circuit. The waveforms can also be used to visually highlight various design aspects. This graphical interface is also referred to as the waveform viewer.
Three major categories of tools are currently available in the market to facilitate the RTL-level simulation and testing of circuit designs. These comprise Model Checking tools, Simulation tools and Waveform viewing tools. A typical example of the RTL Simulation tool is ModelSim™ from Model Technology Inc, VCS from Synopsys. A typical example of the Model checking tool is RuleBase from IBM. A typical example of the Waveform viewing tool is Debussy from Novas Software.
Software RTL Simulators provide a high level of verification and debugging environment but have relatively slow speed and verify only a small fraction of the possible input sequences. They provide good flexibility in terms of design verification and also provide a high-level of abstraction environment for verification and debugging. It is easier to change design parameters and observe the changes in the RTL Simulators. However, for complex designs, the verification requires a large number of test vectors. Test vectors comprise a legal input sequence to a given circuit. This can take a considerable amount of time using software RTL Simulation as contrasted with hardware Acceleration or Emulation starting from a gate-level representation. Furthermore, it may be useful to perform in-situ verification. This comprises validating the design under test by connecting the Emulator or hardware Accelerator to the target system environment (where the design is to be inserted after the design is completed). One disadvantage of the gate-level simulation, however, is that most of the high-level information from the RTL source code is lost. Without the high-level information, many of the debugging functionalities are unavailable.
Currently, effort has been directed towards improving the visualization of the circuits and the various parameters guiding the circuit design. This involves display of various waveforms and expressions corresponding to the characteristic waveform of the signal. The existing waveform viewers such as Debussy and Signalscan have the ability to display the waveform of the signals and also display corresponding expressions in separate windows. Further, these waveform viewers provide an added functionality of adding or dropping an icon representing a collection of signals on the waveform-displaying window. Additionally, it is also possible to display a portion of the source code corresponding to a waveform by clicking on the waveform and vice-versa.
The existing waveform viewers display portions of source code and waveforms in different windows. However, there is a need for a system and method that displays the portions of the RTL source code and the waveform in the same window. This is required to enhance the readability and visualization of the circuit parameters. Further, there is a need for a system and method that provides the reason for a characteristic waveform to a designer. This facility will help the designer to better understand the circuit design (as embodied in the RTL source code) and behavior. Also, there is a need for a system and method that isolates and displays only the portion of the RTL source code (and possibly some surrounding source code to provide context) that correspond to a waveform that the designer desires to see. Also, there is a need to have a means of interactively browsing the RTL source code and debugging problems in the RTL source code in the context of a simulation value database.